This paper uses the theory of stochastic arithmetic as a solution for the FPGA implementation of a complex feed forward, multi layered neural network. Compared with the traditional digital implementations, the stochastic approach simplifies the computation involved and saves digital resources. The architecture combines stochastic computation techniques with a novel Look Up-Table-based that fully exploits the Look Up-Table structure of many FPGAs. Basic operations of simple ANN are mapped into a modular design. The system control module, random pulse generating module , bit stream generating module , LFSR_32(Liner Feedback Shift Register) sub module, modulator sub module, neuron module and bit stream converter module , are described in hardware using a schematic editor of the Foundation 4.1i, which is a software tool from Xilinx. Thus the modules can be parameterized, providing easy scalability of the system to the different applications constraints and requirements. The feasibility of the proposed ANN is demonstrated by testing it using two case studies. The objective of the first test is the to decomposition of Boolean Function sets (AND, OR, EXOR) the simulation results show that the design is able to find the obtainable values for the functions, while, the objective of the second test is to find the frequency recognition for square wave with different frequencies, the simulation results show that the design is suitable for using in this field.