Computer Engineering Dept, University of Technology, Baghdad, Iraq


This research presents a study for multicore Reduced Instruction Set
Computer (RISC) processor implemented on the Field Programmable Gate
Array(FPGA).The Microprocessor without- Interlocked Pipeline Stages (MIPS)
processor is designed for the implementation of educational purposes, as well as it is
expected that this prototype of processor will be used for multimedia or big data
applications. 32- bit MIPS processor was designed by using Very High speed Hardware
Description Language (VHDL). Pipelined MIPS processor contains three parts that are :
data path 32-bit MIPS pipeline, control unit, and hazard unit. The single cycle MIPS
system was subdivided into five pipeline stages to achieve the pipeline MIPS processor.
The five parts include: instruction fetch (IF), Instruction Decode (ID), execution (EXE),
memory (MEM) and Write Back (WB). Three types of hazard: data hazard , control
hazard and strctural hazard are resolved. Certain components in the pipelined stage for
the design processor were iterated for four core SIMD pipelined processors. The MIPS is
developed using Xilinx ISE 14.7 design suite. The designed processor was implemented
successfully on Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA. The total power
analysis of multi-core MIPS processor is obtanined 3.422 watt and the clock period was
7.329 ns (frequency: 136.444MHz).