IRAQI JOURNAL OF COMPUTERS, COMMUNICATIONS, CONTROL AND SYSTEMS ENGINEERING

This research presents a study for multicore Reduced Instruction Set
Computer (RISC) processor implemented on the Field Programmable Gate
Array(FPGA).The Microprocessor without- Interlocked Pipeline Stages (MIPS)
processor is designed for the implementation of educational purposes, as well as it is
expected that this prototype of processor will be used for multimedia or big data
applications. 32- bit MIPS processor was designed by using Very High speed Hardware
Description Language (VHDL). Pipelined MIPS processor contains three parts that are :
data path 32-bit MIPS pipeline, control unit, and hazard unit. The single cycle MIPS
system was subdivided into five pipeline stages to achieve the pipeline MIPS processor.
The five parts include: instruction fetch (IF), Instruction Decode (ID), execution (EXE),
memory (MEM) and Write Back (WB). Three types of hazard: data hazard , control
hazard and strctural hazard are resolved. Certain components in the pipelined stage for
the design processor were iterated for four core SIMD pipelined processors. The MIPS is
developed using Xilinx ISE 14.7 design suite. The designed processor was implemented
successfully on Xilinx Virtex-6 XC6VLX240T-1FFG1156 FPGA. The total power
analysis of multi-core MIPS processor is obtanined 3.422 watt and the clock period was
7.329 ns (frequency: 136.444MHz).

Recently, video files and images have became the dominant media material for transmitting or storing across different applications that are used by different people. So, there was a serious need to find more effective and efficient video compression techniques to reduce the large size of such multimedia files. This paper proposes SIMD based FPGA lossless JPEG video compression system with the facility of scalability. Generally, the proposed system consists of a software side and a hardware side. The digital video file is prepared to be processed by the hardware side frame by frame on the software side. The hardware side is proposed to consist of two main processing circuits, which are the prediction circuit for calculating the predicted value of each pixel in the certain frame and the encoding circuit that was represented by a modified RLE (Run-Length-Encoder) to encode the result obtained through subtracting the predicted value from the real value for each pixel to produce the final compressed video file. The compression ratio obtained for the proposed system is equal to 1.7493. The throughput improvement for the two and four processing units basing on SIMD architecture was 100 MP/s and 200 MP/s, respectively. The clock results showed that the number of clocks required had become 50% and 25% when using two processing units and four processing units, respectively, from the number of clocks using single processing units.

This paper proposes an off-line adaptive digital Proportional Integral Derivative (PID) control algorithm based on Field Programmable Gate Array (FPGA) for Proton Exchange Membrane Fuel Cell (PEMFC) Model. The aim of this research is to obtain the best hydrogen partial pressure (PH2) value using FPGA emulator to design and implement a digital PID controller that track the fuel cell output voltage during a variable load current applied. The off-line Particle Swarm Optimization (PSO) algorithm is used for finding and tuning the optimal value of the digital PID controller parameters that improve the dynamic behavior of the closed loop digital control fuel cell system and to achieve the stability of the desired output voltage of fuel cell. The numerical simulation results (MATLAB) package and FPGA emulator experimental work show the performance of the proposed FPGA-PID controller in terms of voltage error reduction and generating optimal value of the (PH2) control action without oscillation in the output and no saturation state when these results are compared with other control methodology.

Abstract-Depending on the response of the system, digital Filters can be designed
using frequency sampling or windowing methods; but these methods have a problem in
precise control of the critical frequencies. In the sampling method, the weighted
approximation error between the actual frequency response and the desired filter
response is spread across the pass-band and the stop-band and the maximum error is
minimized, resulting ripples in the pass-band and the stop-band. The frequency
sampling method has the same tolerance requirements as the windowing method. In this
work we implemented a digital FIR high pass filter using MATLAB program
(FDATools) using sampling and windowing methods, then the design in the FPGA kit
is downloaded by generating VHDL description. A comparison the amount of the
component has been used in the FPGA for both methods. The FIR filter is implemented
using Spartan 3AN- XC3S700a-4FG484FPGA and simulated with the help of Xilinx
ISE (Integrated Software Environment) Software WEBPACK Project Navigator 11i.

Abstract:
This paper provides a new algorithm for the evaluation of WAVELET
TRANSFORM (WT) and the WAVELET PACKET TRANSFORM (WPT) using Field
Programmable Gate Array (FPGA).
FPGA realization is the most recent category, which takes the place in the
implementation of DSP applications, and it had proved the capability to handle such jobs
and supports the necessary needs of scalability, speed, size, cost, and efficiency.
The WT & WPT coefficients are depend upon the multi resolution analysis approach
using HAAR or DUBCHIES2 bases functions. Next, coefficients are evaluated in the
FPGA card through its implementation using logical circuits using a specified electronic
library kit.

Abstract:
A single layer feed-forward neural network are proposed and implemented using the
schematic editor of the Xilinx foundation series 2.1i. First the mathematical model of the
data set (weights and inputs) is presented in a matrix multiplication format. Secondly the
five design stages are presented and implemented without using the finite state machine,
which control the processes of the forward propagation phase, error calculation, and the
training algorithm. Finally the design can be optimized to decrease the total execution time
and to minimize the cost, which eventually will increase the performance and improve the
function density.