Omar Arif Abdul-Rahman; Hanan A. R. Akkar
Volume 9, Issue 1 , December 2009, , Page 51-71
Abstract
Abstract:
This paper presents a design of a general purpose GA. It is described using the Very high speed integrated circuits Hardware Description Language (VHDL), which is one of the Hardware Description Languages (HDLs). The complete system is implemented in a single Field Programmable Gate Array ...
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Abstract:
This paper presents a design of a general purpose GA. It is described using the Very high speed integrated circuits Hardware Description Language (VHDL), which is one of the Hardware Description Languages (HDLs). The complete system is implemented in a single Field Programmable Gate Array (FPGA) platform using the Foundation 2.1i, which is a software tool from XILINX. The feasibility of the purposed FPGA-based GA (FPGAGA) is demonstrated by testing it using two case studies. The objective of the first test is to maximize mathematical functions (f(x) = 2x, f(x) = x+5 and f(x) =2x3 -45x2 +300x) over the domain . Simulation results show that the adopted design is able to find the maximum obtainable values for all the functions. The objective of the second test is to solve circuit partitioning problem by distributing given modules (or cells) over two blocks. The number of inter-block connections and the number of modules assigned for each block should be minimum. Simulation results show that the final arrangements reached by the FPGAGA for the given arrangements (consist of 5, 10 and 15 modules) is well optimized in term" of the number of inter-block connections and the modules assigned for each block.
